Single Crystal Silicon Thin Film on Polymer Substrate by Double Layer Transfer Method

We report discovery of new method to transfer a single crystal silicon thin film onto a bendable polymer substrate by using layer transfer process. The method includes creation of mechanically weakened layer 100 nm - 600 nm below the Si wafer surface using boron and hydrogen ion implantations. Silicon mother wafer is then pre-bonded to glass and exfoliated. Exfoliation divides the glass-silicon assembly into weakly bound Si thin film on glass and leftover mother Si wafer. Then the silicon thin film was transferred from glass substrate into a polymer substrate.

Source:IOPscience

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High Oxygen Czochralski Silicon Crystal Growth Relationship to Epitaxial Stacking Faults

With larger diameter Czochralski‐grown silicon crystals an increase in the oxygen content is observed. Oxygen in excess of the solubility limit will precipitate resulting in bulk crystal defects which can modify gettering of impurities known to degrade electrical characteristics. In this study we have investigated crystal growth parameters and related them to the properties of the crystal. Wafers were processed from crystals grown under various conditions. Defect formation was evaluated as a function of processing and related to the crystal properties. By growing 2 in. diam crystals at high seed rotation rates so as to maximize the oxygen content, we were able to suppress saucer etch pit formation and epitaxial stacking fault formation. The high oxygen content crystals behaved in the same manner as 3 in. diam crystals with respect to defect formation.

Source:IOPscience

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Gate-Oxide-Integrity Characteristics of Vacancy-rich Wafer Compared with Crystal-Originated-Pits-free Wafer as a Function of Oxide Thickness

The dielectric breakdown of oxides with various thickness between 5–70 nm on Czochralski (CZ)-grown silicon wafer had been investigated. To observe the effects of crystal-originated-particle (COP), vacancy-rich wafers and COP-free wafers were compared. In breakdown voltage (BV) measurement, breakdown fractions of vacancy-rich wafers were increased with the increase of oxide thickness (tOX) and showed a maximum value at the tOX range of 10–20 nm. On the other hand, COP-free wafers showed few breakdowns over all the range of tOX. Furthermore, time dependent dielectric breakdown (TDDB) of the vacancy-rich wafers showed higher extrinsic breakdowns than that of the COP-free wafers in the tOX below 20 nm. For the intrinsic breakdown, two groups showed the same charge-to-breakdown (QBD) along the strength of injection current over all the range of tOX. Especially, only in case of vacancy-rich wafer, abnormal increase of current, i.e., hump phenomena, was observed in the range of electric field below the Fowler-Nordheim (F-N) tunneling.

Source:IOPscience

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Improvement of the Gate Oxide Integrity by Modifying Crystal Pulling and Its Impact on Device Failures

Czochralski single‐crystal wafers grown with different pulling rates using various hot zone modifications were analyzed with respect to grown‐in defects and gate oxide integrity (GOI). The quality of the wafers characterized by crystal defect density as well as by GOI yield was found to be related strongly with the pulling conditions. Depending on the growth rate two concentric regions, characterized by different GOI and grown‐in defect levels and separated by a ring‐like area with high stacking fault density, were found on the wafers. The single‐bit failure rate in some dynamic random access memory (DRAM) reliability tests turned out to correlate with GOI yield. Thus it is clearly shown that the bulk quality related with crystal pulling conditions correlates with the DRAM reliability.

Source:IOPscience

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Single Crystal Silicon‐on‐Oxide by a Scanning CW Laser Induced Lateral Seeding Process

A 1 μm thick layer of silicon dioxide is grown on selected areas of a {100} silicon wafer such that the resulting silicon dioxide surface is coplanar with the surface of the silicon wafer. A 0.5 μm thick layer of polycrystalline silicon is deposited onto the silicon wafer using a low pressure CVD process. By scanning a focused CW argon laser beam onto the area where the polycrystalline silicon is deposited directly on the exposed silicon substrate, the polycrystalline silicon is converted into an epitaxial layer by a liquid phase process. By scanning the laser beam from the epitaxial region to the region where the polycrystalline silicon is deposited on the silicon dioxide layer, the polycrystalline silicon is converted into a single crystal through a zone melting process, where the previously formed epitaxial layer is used as the seed. This process is named "lateral seeding." It is found that the resulting area of the single crystal on the silicon dioxide layer is dependent on the temperature of the substrate and the crystallographic direction of the edges of the oxide layer. The best results are obtained with a high substrate temperature and with the edges of the oxide layers aligned along a <100> direction. Single crystal regions that extended as much as 80 μm from the epitaxial seed region onto the silicon dioxide region have been obtained. It is inferred from the experimental results that a line‐shaped beam with a flat intensity profile is preferred for improved lateral seeding results.

Source:IOPscience

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Growth of 2 inch ZnO bulk single crystal by the hydrothermal method

Zinc oxide (ZnO) single crystals were grown by the hydrothermal method using a platinum inner container. The 2 inch ZnO wafers obtained from these bulk crystals possess an extremely high crystallinity and purity. The electrical resistivity is highly uniform over the entire wafer area. After annealing, the step-and-terrace structure was observed on the surface of the wafer. The etch pit density was decreased to less than 80 cm−2. These results suggest that these 2 inch ZnO wafers are suitable for wide band gap device applications.

Source:IOPscience

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Method to Reduce Crystal Defects in AlCu Bond Pad

AlCu bond pad crystal defect is observed after wafer processing and before die sawing. It affects wire bonding or bump performance resulting in lower bond pull and ball shear force, even adhesion failure. There are many factors contributing to the crystal defect, such as: polymer removal status, storage condition, humidity and fluorine concentration in the environment etc. Up to date, the impact of humidity and fluorine concentration to crystal defect has been broadly studied, but the polymer remover's effect is somewhat unknown. In this paper, two different chemistry based polymer removers are studied to correlate to crystal defect behavior. After processed by the polymer remover, AlCu bond pad wafers are subject to different environment conditions including wet box (44% and 63% humidity separately). Subsequently, each wet box is filled with fluorine at the concentration of 524ug/pod. The crystal defect growth is examined as a function of time using optical methodology. The results reveal that the polymer chemistry is also critical to crystal defect growth as well as the impact on queue time and storage conditions. An optimized fluoride containing polymer remover can substantially lower the crystal defect risk leading to a wider process windows.

Source:IOPscience

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Precise [100] crystal orientation determination on lang110rang-oriented silicon wafers

In this paper we propose a novel pre-etch method to determine the [100] direction on the surface of 110 silicon wafers with a diameter of 100 mm for precise bulk etching. A series of circular windows is arranged in an arc with a radius of 48.9 mm, and bulk etched to form hexagonal shapes for the indication of crystal orientation. The hexagons, which have two angles of 109° and four other angles of 125.5°, are surrounded by four {111} vertical planes and two {111} planes inclined 35.5° to the wafer surface. The corners of the hexagons are used as an alignment reference to indicate the [100] direction on the 110 silicon wafers. Using a calculation from the relationship between the circular windows with different diameters of 153, 74 and 35 μm and the circle center distances of 192, 96 and 48 μm, the alignment accuracy can be determined as ±0.11°, ±0.06° and ±0.03° to the projected [100] orientation, respectively. Experimental results also demonstrate the feasibility of accurately aligning long etching slots along the 111 direction. The misalignment has been determined to be 0.02° from 20 experimental samples, much less than the estimated value of ±0.03° on a 100 mm 110 wafer. This simple, accurate and fast alignment technique is applicable to long slot fabrication on 110wafers with tight geometry tolerance.

Source:IOPscience

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Fabrication of a Grooved Single‐Crystal Silicon X‐Ray Analyzer

Silicon x‐ray analyzer crystals were microfabricated by dicing and etching 10.3 cm (4‐inch) diam, 1.35 mm thick, undoped float zone (111) silicon wafers. These analyzer crystals are intended for a beam line at the Advanced Photon Source synchrotron accelerator ring under construction at the Argonne National Laboratory. Parallel and perpendicular, 1 mm spaced grooves were cut on the silicon wafers using an automated dicing saw. The grooves were cut at 15° and 105° to the '110' primary flat to avoid crystallographic cleavage directions because mechanical strength was desired. The depth of the grooves was 1.15 mm, which was 85% of the wafer thickness. The two cutting parameters, progressive cutting thickness, and feed rate were optimized to reduce saw damage and chipping. Saw damage, which extended over a region of about 30 μm from grooves was removed by isotropic etching. The quality of the single crystal was tested by measuring the width of x‐ray rocking curves with a double‐crystal diffractometer. The best width obtained with 11.2 arc‐s. Since the ideal full width at half maximum (FWHM) according to x‐ray dynamical diffraction theory is 9.7 arc‐s, a broadening function with a FWHM of only 5.6 arc‐s is present due to residual strains (quadrature addition is assumed).

Source:IOPscience

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Crystal Defects in Highly Boron Doped Silicon

Si wafers with boron concentrations up to 2 ⋅ 1019 cm−3 were characterized by delineating defects with SC1 solution and analyzing them with respect to crystal originated particles (COP). No oxidation induced stacking fault (OSF) ring appears, and the whole wafer displays a homogeneous COP density after SC1 treatment for low boron doped ingots in a resistivity range of several ohms centimeter and appropriate pulling conditions. Without modification of the crystal pulling process but increasing boron concentration the radial COP distribution changes. The area with a high COP density shrinks and vanishes in the center of the wafer when the boron concentration approaches a level of about 1019 cm−3. Adjacent to the area of high COP density an OSF ring is found, similar to the case of low boron doped material at reduced pulling rate. It is assumed that boron doping at a sufficiently high level modifies the balance of vacancies and interstitials generated in the crystal pulling process and changes the radial defect distribution in the silicon crystals.

Source:IOPscience

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Status of Large Diameter SiC Single Crystals

Large SiC single crystals, semi-insulating and n-type, up to 150mm in diameter are grown by II-VI Incorporated. In addition to the recent product launch of 150mm substrates, significant improvements have been made in crystal quality. The values of FWHM of x-ray rocking curves are typically 15-30 arc-seconds for 4H SI wafers and 11-25 arc-seconds for 4H n+ wafers. We have achieved 150 mm wafers free of stacking faults and micro pipes with total dislocation density of 2x103 cm-2, TSD density of ~3x102 cm-2, and BPD density of 2x102 cm-2. For semi-insulating wafers we have achieved resistivities in excess of 1E11Ω-cm.

Source:IOPscience

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Laser recovery of grinding-induced subsurface damage in the edge and notch of a single-crystal silicon wafer

The edges and notches of silicon wafers are usually machined by diamond grinding, and the grinding-induced subsurface damage causes wafer breakage and particle contamination problems. However, the edge and notch surfaces have large curvature and sharp corners, thus it is difficult to be finished by chemo-mechanical polishing. In this study, a nanosecond pulsed Nd:YAG laser was used to irradiate the edge and notch of a boron-doped single-crystal silicon wafer to recover the grinding-induced subsurface damage. The reflection loss and the change of laser fluence when irradiating a curved surface were considered, and the damage recovery behavior was investigated. The surface roughness, crystallinity, and hardness of the laser recovered region were measured by using white light interferometry, laser micro-Raman spectroscopy, and nanoindentation, respectively. The results showed that after laser irradiation the damaged region was recovered to a single-crystal structure with nanometric surface roughness, and the surface hardness was also improved. This study demonstrates that laser recovery is a promising post-grinding process for improving the surface integrity of the edge and notch of silicon wafers.

Source:IOPscience

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The Effect of the Crystal Grown‐in Defects on the Pause Tail Characteristics of Megabit Dynamic Random Access Memory Devices

The effect of the crystal grown‐in defects on the pause tail characteristics of megabit dynamic random access memory devices was investigated. By comparing the performance of the devices fabricated on epitaxial silicon wafers with those fabricated on polished Czochralski silicon wafers, it was found that the refresh time of the memory devices fabricated on a polished silicon wafer is strongly affected by the crystal grown‐in defects. Based upon the present results, the refresh time failure of the memory devices could be attributed to several types of crystal defects which include the D‐defects produced as a result of vacancy aggregation during crystal growth and those associated with oxygen precipitation.

Source:IOPscience

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Defects in Silicon Crystals and Their Impact on DRAM Device Characteristics

Polished p-wafers from vacancy-rich silicon crystals are used as substrates for many device applications and, in particular, for memory devices. Octahedral vacancy aggregates, the so-called crystal originated pits, are found in these wafers with sizes of 150 nm and densities of  To meet the design rule requirements of 0.13 μm and below, a reduction of defect size and density is required. The approaches to achieve silicon with nearly no intrinsic point defect aggregates are the growth of so-called perfect crystals, the growth of nitrogen-doped crystals with very fast cooling rates and subsequent high temperature wafer annealing, and epitaxy of wafers. In addition, new concepts like wafers with a thin refinement layer grown on a cost and bulk optimized substrate (so-called fLASH! wafers) will allow further cost reduction. © 2002 The Electrochemical Society. All rights reserved.

Source:IOPscience

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