First Wafer-Scale, Single-Crystal, Monolayer Graphene Made in Bulk

• Samsung’s Advanced Institute of Technology has been at the forefront of applying graphene to electronics, developing such things as zippy new types of transistors.

Despite these efforts, for graphene to succeed at reaching commercial applications in digital electronics a way of producing high-quality monolayer graphene in bulk needs to be developed.

In this week's issue of the journal Science (“Wafer-Scale Growth of Single-Crystal Monolayer Graphene on Reusable Hydrogen-Terminated Germanium”), Samsung along with researchers at South Korea’s Sungkyunkwan University claim to have produced the first wafer-scale growth of wrinkle-free single-crystal monolayer graphene on a silicon wafer.

While there has been another successful demonstration of producing single-crystal monolayer graphene, that method is too costly and cannot be readily adapted to bulk-scale production.

The South Korean researchers overcame this production limitation in a process that used chemical vapor deposition (CVD) method for growing the graphene on the surface of a germanium coated silicon wafer coated. However, in this new method the researchers were able to transfer the graphene from the germanium without resorting to the damaging wet chemical etching process typically used. Instead, the researchers deposited a thin film layer of gold atop the graphene using a thermal evaporator. By then attaching the gold/graphene/germanium combination to a thermal release tape and applying a bit of pressure, the graphene and germanium substrate were easily separated .

Research late last year demonstrated that graphene loses none of its attractive electronic properties, such as high electron mobility, when paired with silicon. So it would appear that Samsung's new technique could help usher graphene into digital electronic applications, where high-quality material is essential.

But the hurdles are high in this field. To win a place in electronics, graphene has to be both cheaper and better than silicon and a host of alternative materials that have years of a developmental head start. For instance, in flexible electronics, which is one of the applications cited as a potential use for Samsung’s new graphene, the material not only has to prove itself better than the specially formulated plastics that currently rule the roost, but also needs to outperform carbon nanotubes, as well.

But you don' t have to wait for graphene to take over the semiconductor scene to see it used in electronics. Lower quality graphene should be just fine forthermal management systems and supercapacitors for portable electronics that would not just power the devices but serve as a high-frequency filter.

Keywords:  Samsung band gap carbon nanotubes chemical vapor depositiondigital electronics flexible electronics graphene silicon

Source: www.ieee.org

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Single crystal diamond wafers for high power electronics

Highlights

•Presentation of a clear target for the R&D of diamond wafer for power electronics application.

•Required target properties for first stage diamond wafers are; a killer defect density less than 0.1cm-2, resistivity less than 0.005Ωcm and a size of 4 inch.

•For the final commercialization stage, targets of zero killer defects, resistivity of 0.001Ωcm and a size of 6 inch size are proposed.

According to international energy proposal, about 25% of the total CO2 reduction should come from “end use efficiency”. Hence, low loss power devices are an important technology for the 21st century. Diamond-based devices have the potential, but this would require fast development in order to contribute to the CO2 reduction plan early in this century. Here, we present a clear target for the R&D of diamond wafer. According to the expected applications of diamond devices with a vertical structure, the required target properties for first stage diamond wafers are; a killer defect density less than 0.1 cm^− 2, resistivity less than 0.005 Ω cm and a size of 4 in. For the final commercialization stage, targets of zero killer defects, resistivity of 0.001 Ω cm and a size of 6 in. are proposed. The challenges and proposal solutions are reviewed for each technology.

Graphical abstract

Keywords:  Single crystal diamond;  Diamond wafer;  Power device

Source: Sciencedirect

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A predictive model of grinding force in silicon wafer self-rotating grinding

Highlights

•Grinding force model in silicon wafer self-rotating grinding is established.

•The model reveals the effect of grinding parameters on grinding force.

•Grinding force model is adopted to control grinding damage of silicon wafer.

Silicon wafer thinning is mostly performed by the method of self-rotating grinding. In grinding, the grinding force is a crucial factor of affecting the grinding performance, form accuracy and surface/subsurface thinning quality. To control the thinning quality of ground wafer, grinding force is the most essential factor need to be controlled. However, no theoretical model is developed to correlate grinding parameters to grinding force yet. In this article, a theoretical model is established based on the removal behavior of silicon, including cutting and sliding. For the first time, the effects of processing parameters, wafer radial distance and crystal orientation on grinding force are quantitatively described in a theoretical model. Excess grinding force causes local damage of wafer in the form of subsurface cracks, as a determinant factor on the quality of wafer. Therefore, nine sets of self-rotating grinding experiments with variable processing parameters are performed, and the depth of subsurface cracks h are measured to evaluate the damage of ground wafer. Based on the scratching theory of single abrasive grain, the relationship between h and the normal grinding force F_nt is found, which is also validated by the experimental results. Finally, an optimized two-stage process is proposed to control subsurface cracks and improve material removal rate simultaneously, according to the predictive model of grinding force.

Keywords:  Silicon wafer;  Grinding force;  Thinning process;  Process parameters;  Subsurface crack;  Optimized process

Source: Sciencedirect

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Temperature dependent ferroelectric and ferroelastic behaviour of PZT wafers

A study is carried out to understand the temperature dependent non-linear behaviour of PZT wafers under electrical and mechanical loading. Experiments are conducted on PZT wafers at room and elevated temperatures under a high cyclic electric field to examine their behaviour. Experimental characterization is also extended to pure mechanical loading (uni-axial compressive stress) condition at room and elevated temperatures. A temperature dependent micro-mechanical model is proposed based on internal energy to evaluate the ferrolectric and ferroelastic behaviour of PZT wafer. The developed model is incorporated into a 3D finite element framework and numerical simulations are performed. The simulated results for electrical loading are compared with experimental observations which show a significant decrease in dielectric response at elevated temperature and it is also observed that the operating temperature influences the electrical displacement and strain along poling direction (thickness direction) under mechanical loading. A parametric study has also been conducted to understand the performance of PZT wafer in which macro-state variables such as remnant polarization, remnant strain, maximum polarization, and maximum strain are extracted and discussed as a function of temperature.

Keywords:  PZT wafers;  Electrical loading;  Mechanical loading;  Internal energy based switching criteria

Source: Sciencedirect

If you need more information about crytal wafer, please visit our website: http://www.powerwaywafer.com/SiC-Substrate.html, send us email at powerwaymaterial@gmail.com.