Dec 7, 2015

Developments of elemental technologies to produce inch-size single-crystal diamond wafers


Seen as the future of wide band gap semiconductor materials, single-crystal diamonds need to be fabricated in at least inch-size wafers if they are to be of use in industry. The key methods required to achieve this are 1) improving the growth of single crystals with sufficient quality over large areas at an acceptable growth rate, 2) enlarging the seed crystal, and 3) improving the fabrication of the freestanding wafers. This paper briefly reviews recent progresses and reports the most recent results of our research of solving these technical problems.

Research Highlights

► By using a lift-off process with ion implantation, we fabricated clone substrates. ► These clones are found to be useful to fabricate 1 inch mosaic wafers. ► The lift off process is applied also to make several clones of this 1 inch wafers. ► Some characterizations imply their quality is close to those of HPHT substrates.


  • Single-crystal-diamond
  • Bulk-crystal-growth
  • Freestanding wafer
  • Simulation
  • Mosaic wafer

    • Source:Sciencedirect

Nov 25, 2015

Vertically Conductive Single-Crystal SiC-Based Bragg Reflector Grown on Si Wafer

Single-crystal silicon carbide (SiC) thin-films on silicon (Si) were used for the fabrication and characterization of electrically conductive distributed Bragg reflectors (DBRs) on 100 mm Si wafers. The DBRs, each composed of 3 alternating layers of SiC and Al(Ga)N grown on Si substrates, show high wafer uniformity with a typical maximum reflectance of 54% in the blue spectrum and a stopband (at 80% maximum reflectance) as large as 100 nm. Furthermore, high vertical electrical conduction is also demonstrated resulting to a density of current exceeding 70 A/cm2 above 1.5 V. Such SiC/III-N DBRs with high thermal and electrical conductivities could be used as pseudo-substrate to enhance the efficiency of SiC-based and GaN-based optoelectronic devices on large Si wafers.

Growth of single-crystal silicon carbide on silicon substrate (SiC-on-Si) is seen as a very attractive approach to combine the excellent properties of SiC with the low cost, large wafer size and well-developed micro-machining of Si wafers. Despite their large lattice and thermal expansion mismatches, both around 20%, uniform and crack-free single-crystal SiC-on-Si templates can be obtained with a relatively good crystal quality1. Consequently, SiC-on-Si pseudo-substrate are now investigated for a broad range of applications including photonic, gallium nitride based (GaN) devices on Si, micro-electro-mechanical systems (MEMS) and graphene epitaxial growth.
We propose and demonstrate for the first time the use of the SiC-on-Si technology to fabricate a vertically conductive single-crystal distributed Bragg reflector (DBR) on Si substrate. Such SiC-based DBRs enable the monolithic integration of efficient GaN-based optoelectronic devices on large Si wafers. SiC is indeed commonly used as growth substrate for commercial high power GaN devices as it has the smallest lattice mismatch amongst all foreign substrates for the hetero-epitaxy of III-nitride compound semiconductors, typically less than 4%. However, as SiC substrates are smaller and much more expensive than Si substrates, the SiC-on-Si technology is economically very attractive for the monolithic integration of GaN devices on large Si wafers. Several demonstrations of GaN light emitting diodes (GaN-LEDs) and GaN power devices grown on SiC-on-Si substrates have already been reported4,5. By using Si as a platform technology, GaN devices can also be directly integrated with CMOS devices and depreciated CMOS factory plants can be utilized, which lead to substantial cost saving in capital equipment investment and device fabrication costs. Thanks to its high electrical and thermal conductivities, combined with a large refractive index (RI) and a low absorption in the visible spectrum, SiC is also a material of choice for the fabrication of single-crystal DBRs on Si operating in the visible or the infrared (IR) spectra. Light extraction (or absorption) efficiency of an optoelectronic device can be greatly improved with a DBR when used as a rear mirror sandwiched between the Si substrate and the device structure. It is therefore very attractive to develop a SiC-based DBR for GaN-LEDs on Si. Another advantage of monolithic DBR-LEDs on Si would be to greatly simplify the device processing, and thus to reduce the manufacturing cost, compared to the standard GaN-LED on Si technology. Indeed, because of the strong optical absorption occurring in the Si substrate, manufacturing of high brightness (HB) LEDs on Si currently requires the removal of the Si growth substrate followed by the transfer of the III-N epilayers to a new high reflective carrier. This process is particularly difficult and expensive to apply on large substrates as it requires low wafer bowing and often expensive gold-based bonding layer, hence lowers the process yield and induces a high manufacturing cost.
A DBR consists of multiple transparent layers with alternative high and low RI, and with each layer thickness carefully chosen to create an optical resonance effect at the desired wavelength. DBRs are fundamental for the fabrication of many photonic and optoelectronic devices using optical resonance effects in a microcavity. Such devices include Fabry-Perot filters and modulators, resonant cavity (RC)-LEDs and vertical cavity surface emitting lasers (VCSELs). Monolithic growth of a DBR for GaN devices on Si requires the use of transparent materials which are compatible with both Si and III-N semiconductors, strongly limiting the number of suitable candidates. Most of the demonstrations of DBR for GaN-devices (mainly targeting LED applications) on Si have been made using only III-N semiconductors as the constitutive layer. Reflectance as high as 95% was achieved, but as many as 20 pairs AlInN/GaN were needed because of the small RI contrast achievable between those III-N semiconductor layers. Growth of such thick stack of layers implies also the use of complex stress management during the heteroepitaxy on Si because of the large lattice mismatch, making it challenging to grow crack-free DBR-LEDs. So far, the only successful report of such DBR-LED on Si was achieved only by using DBRs with a small number of pairs and thus with a relatively low reflectance. Another drawback with III-N DBRs comes from their weak thermal and electrical conductivities which strongly limit their attractiveness for HB-LEDs. Rare-earth-oxides based DBRs paired with Si thin-films have also been investigated as the high RI contrast allows high reflectivity and large stopband in the visible with just few pairs. However, their detrimental thermal and electrical properties strongly limit their potential for HB-LEDs as well.
In this paper, vertically conductive DBRs, using single-crystal SiC thin-films paired with doped or undoped Al(Ga)N layers, were heteroepitaxially grown on large Si substrates. High uniformity over 100 mm Si wafers, with a typical average peak reflectance of ~55% centered in the blue wavelengths and a stopband of 100 nm, is demonstrated using 1.5 DBR pairs. Furthermore, the DBR structure using Si-doped AlGaN shows very good vertical electrical conductivity, with current density as high as 70 A/cm2 at 1.5 V, without visible degradation of the optical performance compared to its non-conductive counterpart. Such DBR structures with high electrical conductivity of materials with high thermal conductivity are ideal candidates for the monolithic integration of SiC-based and GaN-based high power optoelectronic devices on Si.

Advantages of the SiC-on-Si pseudo-substrate

The DBR structures are composed of a half-wavelength (λ/2)-thick SiC layer, followed by 1 pair of quarter-wavelength (λ/4)-thick AlN/SiC layers (DBR A) or AlGaN/SiC layers (DBR B) as illustrated in Fig. 1. Starting the DBR growth with a SiC layer, instead of directly with the III-N layer, enables the circumvention of several drawbacks of the III-N growth on Si. Firstly, a III-N deposition on SiC should yield an higher crystalline quality than directly on Si thanks to a lower lattice mismatch of 3% compared to 17%. In addition, stress management for the whole heteroepitaxy should also be easier to engineer due to the lower lattice and thermal mismatch. Secondly, an important advantage of the SiC template is to protect the Si substrate from the “melt-back etching” that would otherwise occur due to the formation of a low temperature eutectic between Ga and Si and thus eliminating the need of the usual protective AlN buffer layer with its detrimental current blocking effect. Indeed, AlN is not only intrinsically highly resistive but also induces a large band discontinuity at the Si interface strongly impairing the vertical current flow19. In other words, by starting the DBR growth with a highly conductive SiC layer, it can both protect the Si substrate from reacting with Ga and provide a high electrical conductivity for vertical current injection. Vertical current injection is important because it is the most efficient current scheme for optoelectronic devices such as GaN-LEDs. As SiC has a higher refractive index than Al(Ga)N, the SiC template thickness must be equal to λ/2 to avoid an anti-reflection effect and thus acts as an absentee layer. We emphasize that because of the temperature limitation imposed by the melting point of Si at 1420 °C, only the cubic crystalline structure of SiC, called cubic polytype (or 3C-SiC), can be grown on Si with the LPCVD technique as used in this work1.

Figure 1: Schematic of a SiC/Al(Ga)N DBR structure on Si substrate.
Figure 1
Full size image

Optical constants

Design of a DBR structure requires the knowledge of the optical constants of each constitutive layer. Figure 2(a,b) show the dispersion, deduced from spectroscopy ellipsometry, of RI and of the coefficient of absorption (α) respectively, for the 3C-SiC and nitride thin-films. Data for each material were averaged from fitting made on several test samples and then used to optimise the design of the SiC-based DBRs. AlN and AlGaN layers gave very similar ellipsometric results with no absorption over the investigated spectral range and the dispersion of RI is similar to reported values for AlN thick-films grown on bulk SiC, indicating that a good crystal quality nitride layer has been grown on the SiC-on-Si pseudo-substrate. For convenience, the same RI dispersion for both nitride materials deposited on the SiC template was chosen. 3C-SiC layers grown on Si or on a nitride layer gave similar dispersion of RI, with values in good agreement with reported data for 3C-SiC material. As a result, between 3C-SiC and Al(Ga)N, one obtains a large RI contrast of 0.65 in the blue spectrum which is already 2 to 3 times larger compared to values obtained with the standard pure nitride-based DBRs. Analysis of the optical absorption shows a strong difference between 3C-SiC layers grown on Si and Al(Ga)N. For SiC deposited on Si, there is a significant and increasing residual absorption above 500 nm, whereas SiC deposited on Al(Ga)N show no detectable absorption above 550 nm. As 3C-SiC has an indirect bandgap of ~2.4 eV, any absorption below this energy (i.e. above 520 nm) is induced by sub-bandgap traps created by the crystalline defects. Because of the large lattice mismatch, SiC layers grown on Si have large density of defects, up to 1010 cm−3, leading to the residual absorption detected on the SiC on Si layers1. On the other hand, the lower lattice mismatch between SiC and III-N semiconductors is expected to provide much better crystalline quality resulting in a lower residual absorption as seen in our SiC grown on nitride layer.

Figure 2

Figure 2
Dispersion of the refractive indices (RI) (a) and coefficients of absorption (α) (b) for the single-crystal layers constituting the DBRs on Silicon substrate.
Full size image

Nov 5, 2015

GaAs solar cell on Si substrate with good ohmic GaAs/Si interface by direct wafer bonding


We report wafer bonding (WB) techniques giving good ohmic interfaces of GaAs/Si.
WB with a low bonding temperature and short processing time was performed.
We demonstrated the GaAs solar cell on Si substrate by WB techniques.
Fabricated GaAs solar cell on Si exhibited a comparable performance with that on GaAs.
We proved the feasibility of stable WB technologies of GaAs/Si substrates.


In this work, we developed wafer bonding techniques to bond GaAs and Si wafers. Wafer bonding was carried out at room temperature without high temperature annealing processes. The bonded interface showed a low interface resistance of 8.8×10−3 Ω cm2. We also exploited the new bonding techniques to fabricate a GaAs solar cell on a Si substrate. The solar cell showed a high energy conversion efficiency (13.25%) even without an anti reflection coating. The performance of the fabricated GaAs/Si solar cell was comparable to that of a homogeneous GaAs solar cell grown on a GaAs substrate. *Corresponding author.


Oct 27, 2015

Plastically deformed Si-crystal wafers for neutron-monochromator elements

Plastically deformed Si-crystal wafers were characterized by monochromatic neutron diffraction. During the cylindrically curved deformation, a resolution-limit Bragg peak changes into a box-type angular profile in accordance with the bulk curvature, associated with an enhancement in the angle-integrated intensity (Iθ). Stacking such wafers is efficient in amplifying Iθ further. We propose an application to neutron-focusing monochromator (or analyzer) crystals in order to design a quite compact spectrometer.


Oct 10, 2015

A study on separating of a silicon wafer with moving laser beam by using thermal stress cleaving technique

This study describes the characteristics of separating a silicon wafer with a moving Nd:YAG laser beam by using a thermal stress cleaving technique. The applied laser energy produces a thermal stress that causes the wafer to split along the irradiation path. The wafer separation is similar to crack extension. In this study, the micro-groove was prepared at the leading edge of the silicon wafer to facilitate the fracture. In order to study the thermal effect in the separating process, the temperature at the laser spot was measured by using a two-color pyrometer with an optical fiber, and the mechanism of crack propagation was observed by using an acoustic emission (AE) sensor. The influence of the micro-groove length and depth was also examined. Thermal stress distribution was calculated using the finite-element method (FEM) by considering the temperature from the experimental result. The result indicates that the wafer separation occurred in two stages, fracture initiation and intermittent crack propagation. A higher temperature resulted in faster fracture initiation and higher repetition of the crack propagation signal. The wave mark on the cleaved surface was consistent with the AE signal. The influences of laser power, temperature and the groove parameters to the fracture initiation, crack propagation and cleaved surface features are explained based on the experimental results, while the thermal stress condition is clarified with FEM analysis.


  • Thermal stress cleaving
  • Two-color pyrometer
  • Acoustic emission (AE)
  • Silicon wafer;
  • Cleaving temperature
  • Finite-element method (FEM)

Sep 10, 2015

Transparent and electrically conductive GaSb/Si direct wafer bonding at low temperatures by argon-beam surface activation


Direct, argon-beam activated n-GaSb/n-Si wafer bonding established.
GaSb deoxidation without altering the surface topography.
Fully bonded wafer pairs with high bonding strengths.
Optical transparency of the boundary layers.
Low interface resistivities <5 mΩ cm2 by optimization of the process parameters.


Direct wafer bonds of the material system n-GaSb/n-Si have been achieved by means of a low-temperature direct wafer bonding process, enabling an optical transparency of the bonds along with a high electrical conductivity of the boundary layer. In the used technique, the surfaces are activated by sputter-etching with an argon fast-atom-beam (FAB) and bonded in ultra-high vacuum. The bonds were annealed at temperatures between 300 and 400 °C, followed by an optical, mechanical and electrical characterization of the interface. Additionally, the influence of the sputtering on the surface topography of the GaSb was explicitly investigated. Fully bonded wafer pairs with high bonding strengths were found, as no blade could be inserted into the bonds without destroying the samples. The interfacial resistivities of the bonded wafers were significantly reduced by optimizing the process parameters, by which Ohmic interfacial resistivities of less than 5 mΩ cm2 were reached reproducibly. These promising results make the monolithic integration of GaSb on Si attractive for various applications.


  • Direct wafer bonding
  • Argon-beam surface activation
  • Gallium antimonide;
  • Heterojunction
  • Carrier transport

1. Introduction

The monolithic integration of III–V semiconductors on silicon offers a wide range of innovative applications, like in the fields of power electronics [1], photonics [2] and photovoltaics [3] and [4]. III–V layers on silicon allow combining favorable material characteristics of compound semiconductors with the low-cost, the mechanical stability and the advantages in the processing of silicon. Hence, direct wafer bonding between GaAs/Si [4] and [5] and InP/Si [5] and [6] was investigated extensively in the past years. Likewise, GaSb offers a wide choice of promising and unique characteristics such as small effective masses, high electron and hole mobilities and a band gap suitable for long-wavelength optical devices [7] and [8]. In this paper, we report about the development of a direct wafer bonding process for the formation of transparent and electrically conductive GaSb/Si heterojunctions with promise for the integration of antimonide layers on silicon. The low-temperature bonding process, which was used, is carried out mainly analog to the approach of Suga et al., which was first published in 1992 for the formation of Al/Al and Al/Si3N4 wafer bonds [9].
The activation of the semiconductor surfaces is achieved by removing of the oxides and contaminations by sputtering with an argon beam in a vacuum environment of the reactor chamber (<3 × 10−6 Pa). At the same time, the crystal lattice is destroyed in the first few nanometers creating an amorphous layer [10]. The polished wafers are pressed together, bringing the activated surfaces in close contact. This enables dangling bonds on the surfaces to form covalent bonds, permanently joining the semiconductors [11] and [12].

2. Experimental

An Ayumi SAB-100 wafer bonder was used to bond 4 in. monocrystalline Si wafers to 2 in. monocrystalline GaSb wafers. The bonder contains two saddle field FAB sources, where the Ar atoms are first ionized, then accelerated and finally neutralized. In this setup, the energy of the argon atoms is approximately 0.4–0.6 times the product of the elementary charge and the acceleration voltage. The 300-μm thick Si wafers with an (1 0 0) orientation received a thermal phosphorous diffusion, leading to an n-type doping of 1 × 1020 cm−3 within the first 50 nm. A 500-nm thick GaSb epitaxial layer with an n-type (Te) doping of 1 × 1018 cm−3 was grown onto the GaSb wafers, which have an orientation of (1 0 0) 4° off towards (1 1 1) A. This doping concentration is in the range of the highest active doping concentration achievable for n-type GaSb [13]. A high surface carrier concentration is beneficial to overcome potential barriers at the interface, thus achieving a high conductivity over the heterojunction.
An essential condition for a successful process is, that the wafer surfaces have a RMS roughness <1 nm [14]. This was accomplished by means of chemical-mechanical polishing, resulting in a RMS roughness of 0.2 ± 0.03 nm for the Si substrates and of about 0.5 ± 0.05 nm for the GaSb substrates. No further surface cleaning treatment was applied prior to the bonding process. Furthermore, it is elementary that the roughness is not significantly increased by the FAB treatment.
Therefore the influence of the Ar bombardment on the GaSb surface was investigated using different durations of the sputter treatment (between 2 and 60 min) and argon acceleration voltages (500, 620 and 740 V). The RMS roughness of the GaSb surfaces was measured before and after the sputter-etching at 5 random locations of the sample by means of atomic force microscopy (1 μm × 1 μm scan fields with a resolution of 512 × 512 pixels).
Several bonds were processed, at which some essential process parameters were varied. This includes the temperature during the sputter-etching (20 and 120 °C), which represents also the bonding temperature at which the wafers are pressed together. Furthermore, the acceleration voltage of the Ar ions (500, 620 and 740 V) and the duration of the sputtering on the GaSb wafers (4, 8 and 12 min) were varied. The Si substrates were always sputtered for 8 min with an Ar acceleration voltage of 620 V. The anode current, which correlates to the sputter dose [15], was kept constant at a value of 50 mA. The wafers were pressed together directly after the activation for 5 min with a force of 10 kN, to overcome remaining variations of the wafer thicknesses. Lastly, the temperature of the post-annealing treatment was varied (1 min at 300, 350 and 400 °C).
The bond interfaces were macroscopically investigated for the presence of voids by means of scanning acoustic microscopy (SAM) [16] using a frequency of 100 MHz for the measurement. The optical transparency of the bonds was examined via spectrometric transmittance measurements using a PbS detector, which is sensitive for light up to 2.5 μm. The bonding strengths were investigated with the Maszara crack-opening method [17] and the electrical carrier transport over the GaSb/Si interface was investigated by dark IV-measurements. For this purpose, the bonded wafers were metallized on both sides and diced into 3 mm × 3 mm pieces, which were then post-annealed, as described above. A Ti/Pd/Au/Ag contact was chosen for n-GaSb and a Ti/Pd/Ag contact for n-Si. The actual resistance and IV-characteristic of the bond interface was determined, by subtracting the Ohmic metal contact and substrate resistances from the measured resistance of the metallized sample.

3. Results and discussion

3.1. GaSb surface roughnesses after deoxidation

Fig. 1 shows the resulting RMS roughness of the GaSb wafer surfaces after deoxidation by sputter-etching with varying durations of the Ar beam exposure and acceleration voltages.
Summary of the RMS roughness of the GaSb surfaces after sputtering with varying ...
Fig. 1.
Summary of the RMS roughness of the GaSb surfaces after sputtering with varying durations of the Ar-beam exposure and acceleration voltages.
It was found that within the first 10 min sputtering, the RMS roughness is not increased due to the sputtering with argon atoms accelerated at a voltage of 620 V. After 20, 40 and 60 min of the sputter treatment, the roughness increases to 0.7, 1.3 and 2.1 nm, respectively. As GaSb exhibits different binding energies for Ga and Sb in its crystal structure (Ga: 18.6 eV, Sb: 31.7 eV [18]), this behavior can be explained by selective sputtering of the GaSb, which becomes noticeable at longer sputtering durations after the oxide is already removed. Malherbe et al. reported on a comparable selective sputtering behavior of InP [19]. In this case, the phosphide is preferentially sputtered and the mainly unbound indium on the surface forms agglomerations in an atomic scale.
With the use of an increased acceleration voltage of 740 V, the RMS roughness is already increased after 10 min of FAB treatment to a value of 0.9 nm, as there is extended damage induced by the higher energy of the argon atoms. An even lower acceleration voltage of 500 V on the other hand, leads to no measurable change of the roughness as it was the case for 620 V.
These findings are also represented by exemplary AFM images of the GaSb surface, which are shown in Fig. 2.
AFM images of the GaSb surface topography after: no sputtering treatment (a), ...
Fig. 2.
AFM images of the GaSb surface topography after: no sputtering treatment (a), 10 min sputtering with an acceleration voltage of 620 V (b), 10 min sputtering with an acceleration voltage of 740 V (c) and 60 min sputtering with an acceleration voltage of 620 V (d).
According to the changes of the RMS roughnesses, there is no significant altering of the GaSb surface topography after 10 min sputtering with an acceleration voltage of 620 V (Fig. 2(b)) compared to a polished GaSb surface without any sputter-etching (Fig. 2(a)). On the other hand, after 10 min sputtering with 740 V (Fig. 2(c)) or 60 min sputtering with 620 V (Fig. 2(d)) the altering of the wafer surface becomes obvious.
In the case of silicon, it was shown by Essig et al. and Howlader et al. that the RMS roughness is not altered by the Ar atom bombardment using comparable atom energies and doses [4] and [20].

3.2. Characterization of the GaSb/Si wafer bonds

The GaSb and Si wafers could be bonded successfully with all process parameters, except when an increased acceleration voltage of 740 V was used for the activation of the GaSb surface. In this case, the wafers could not be bonded, which can be explained by the roughening of the GaSb surface after the sputter-etching at an increased acceleration voltage (see Fig. 2(c)).
In general, the wafer bonds reveal only small circular areas which were not bonded due to the presence of particles. Otherwise, the bonds were complete up to the rounded bevel edge of the GaSb wafer. In Fig. 3, an exemplary SAM image of a GaSb/Si bond is shown. Here, both wafer surfaces were activated for 8 min with an Ar acceleration voltage of 620 V.
SAM image of an exemplary GaSb/Si bond. The darker region indicates the bonded ...
Fig. 3.
SAM image of an exemplary GaSb/Si bond. The darker region indicates the bonded area, as the light spots indicate the not bonded areas, where a higher reflection of the acoustic wave at the boundary surface is prevalent.
It was not possible to determine the bond strengths by the Maszara crack-opening method as the blade could not be inserted in the bond interfaces without destroying the GaSb substrate. This was the case for all successful bonded wafer pairs and speaks for a strong and mainly covalent bond at the interface, resulting in high bond energies, which are comparable to the energies in the GaSb bulk crystal. This effect was also reported by Kopperschmidt et al. for hydrophobic GaAs/Si bonds, which were annealed at 850 °C [21].
For the verification of the optical transparency of the GaSb/Si bond interfaces, the spectral transmittance of bonded GaSb/Si wafer pairs was compared with the transmittance trough sole GaSb and Si wafers. It showed that there is no significant absorbance of light intensity in the bond interface. This corresponds to the expectations, as the direct bonding process should not induce any absorbing layers at the boundary interface [10] and [11]. Yet, it has to be noted that GaSb is absorbing until a wavelength of about 1750 nm, so just light with a higher wavelength could be measured.
In Fig. 4IV-curves of the metallized samples are shown for a bonding (and deoxidation) temperature of 120 °C and different post-annealing steps at 300, 350 or 400 °C for 1 min each. One further IV-curve is shown for a bonding temperature of 20 °C with an annealing of 1 min at 350 °C.
IV-characteristics of n-GaSb/n-Si wafer bonds, which were processed at different ...
Fig. 4.
IV-characteristics of n-GaSb/n-Si wafer bonds, which were processed at different bonding and annealing temperatures.
Table 1 shows the interfacial resistivity after the bonding for different process parameters. The calculation of these values is based on the dark IV-curves. The resistivity for the bond processed at 20 °C was calculated in the mostly linear region of ±0.1 V (compare with Fig. 4). As standard parameters for the bonding process, a bonding temperature of 120 °C, an acceleration voltage of 620 V, an Ar beam exposure duration of 8 min were chosen. All variations from these parameters are listed in Table 1. The stated error takes into account uncertainties for the measurement of the metal contact, substrate and bond interface resistance.
Table 1.
Electrical interface resistances of GaSb/Si bonds, depending on the process parameters.
Bond resistances (mΩ cm2) after 1 min post-annealing at

300 °C350 °C400 °C
Bonding temperature
 20 °C35.6 ± 5.316.6 ± 3.524.9 ± 5,1
 120 °C4.4 ± 2.22.2 ± 2.110.3 ± 3.5

Argon acceleration voltage
 500 V20.4 ± 3.78.6 ± 2.913.7 ± 3.8
 620 V4.4 ± 2.22.2 ± 2.110.3 ± 3.5
 740 V

GaSb sputter duration
 4 min5.7 ± 2.33.8 ± 2.528.7 ± 5.4
 8 min4.4 ± 2.22.2 ± 2.110.3 ± 3.5
 12 min1.5 ± 1.81.8 ± 2.37.6 ± 3.2
Despite the high bond strength, non-linear Schottky diode like IV-characteristics were found for all samples bonded at 20 °C room temperature. This can be correlated with the formation of a potential barrier exceeding ∼3kBT prevalent at the boundary interface [22]. According to Bengtsson et al., such a barrier in the conduction band may be formed by acceptor-like defects [23] and explained by the amorphous layer created during the FAB activation process. Carriers are trapped in the defect states, hindering them to contribute to the electrical conductivity. Differences in the electron affinities of GaSb and Si do not explain the diode like IV behavior as both material have similar electron affinities (4.06 eV for GaSb and 4.05 eV for Si [24]). It can be assumed, that with a higher bonding temperature, the defect density is reduced and in fact, we have observed an Ohmic IV-characteristics for the GaSb/Si bonds at 120 °C (compare Fig. 4) with interface resistivities of <5 mΩ cm2, as it is listed in Table 1. This low resistivity speaks for a high amount of covalent bonds at the interface [25].
Besides the influence of the temperature during bonding and deoxidation, also the temperature of the annealing step after bonding has a strong effect on the conductivity. In Fig. 4, it is shown, that the bond resistance decreases, when the samples are annealed for 1 min at 350 °C instead of 300 °C. It has been already observed for direct bonds between GaAs and Si, that the amorphous layer at the interface is partly recrystallized during annealing, resulting in lower resistances [4]. Surprisingly, all samples annealed at 400 °C show a higher bond resistance (compare Table 1). A negative effect of such a high temperature annealing could be induced thermal damage, resulting from the difference in the thermal expansion coefficient (7.8 × 10−6 K−1 for GaSb and 2.6 × 10−6 K−1 for Si [26]). When an annealing temperature of 400 °C is used, the negative effect of a higher annealing temperature seems to outbalance its positive influence.
It was found, that with the use of an acceleration voltage of 500 V the bond resistivity increases compared to the use of voltage of 620 V. It is possible, that the oxide on the GaSb surface was not completely removed within 8 min sputter treatment with an acceleration voltage of 500 V. Zhou et al. showed that remaining oxides at the bond interface hinders the carrier transport, thus increasing the surface resistivity [27]. The bonding at an elevated Ar acceleration voltage of 740 V was not successful, due to the roughening of the surface described above.

4. Summary and conclusion

In conclusion, we have demonstrated direct GaSb/Si wafer bonding after argon-beam surface activation. It was shown that surface roughening of the polished GaSb wafers can be avoided with a sputter-etching treatment of up to 10 min. Fully bonded GaSb/Si wafer pairs with high bond energies were found, which are comparable to the bulk energies in the GaSb crystal. With the optimized process parameters of a bonding temperature of 120 °C, an Ar acceleration voltage of 620 V and a 1 min annealing step at 350 °C, it was possible to achieve a reproducible Ohmic carrier transport over the bond interface with resistivities <5 mΩ cm2 independently of the GaSb sputtering duration of 4, 8 and 12 min. Together with the high bond energies, these low resistivities speak for a high amount of covalent bonds at the interface. With these characteristics of the bond, the presented wafer bonding process is suitable for various advanced applications in high speed electronics or long-wavelength optical devices like for multi-junction solar cells.